A power converter uses a pulse width modulation (PWM) controller to modulate the duty of the power converter in order to regulate the output voltage of the power converter. In further detail, the duty of a power converter modulated by a PWM controller will determine the on time of the power switch in the power supply unit (PSU) or power stage of the power converter. At a regular PWM controller, there is usually a current sense input to implement current limit or total power limit of the power converter. If the current sense input is short, the current limit or total power limit protection is useless. Safety concern happens since there is no power limit to the PSU. The PSU may operate at over power till it burns out.
FIG. 1 is a perspective diagram showing the current mode control of a PWM controller, in which an error signal Vcomp represents the difference between the output voltage of the power converter and a target value, a current sense input Vcs is a feedback signal of inner loop of the PWM controller and represents the output current of the power converter, and a driver output Vgate is produced by the PWM controller for switching the power switch in the PSU. In normal operation, through an SR flip-flop 10, Vgate is triggered by a clock CLK and is ended depending on the comparison result of a comparator 12 comparing Vcs and Vcomp. A protection circuit 14 uses a comparator 16 to compare Vcs with a limit voltage Vlimit which determines the over current threshold of the power converter. Vcs rising to cross over Vlimit will trigger the output of the comparator 16 to reset the SR flip-flop 10, thereby turning off Vgate. If the current sense input Vcs is too small or zero, the power converter would operate at the maximum duty of Vgate and in burst mode. The output is regulated by the external voltage loop without any over power protection.
FIG. 2 is a perspective diagram showing the voltage mode control of a PWM controller, in which in normal operation, the driver output Vgate is also triggered by a clock CLK and is ended depending on the comparison result of a comparator 12 comparing the error signal Vcomp with a ramp signal Ramp. Similarly, when the current sense input Vcs rises to cross over the limit voltage Vlimit which determines the over current threshold of the power converter, the output of the comparator 16 will reset the SR flip-flop 10 so as to turn off Vgate. The current sense input Vcs is as the current limit of the power switch. If Vcs is zero, there is no total power protection.
As shown in FIGS. 1 and 2, the PWM controller relies on the comparator 16 monitoring the current sense input Vcs to provide over current or over power protection. In a conventional PWM controller, no matter using current mode control or voltage mode control, if there is no protection of Vcs=0, the current limit or total power limit would be un-functional.
Therefore, it is desired a detect circuit and protection logic to prevent such failure.